Multi-layered gate for a CMOS imager

ABSTRACT

A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

FIELD OF THE INVENTION

[0001] The present invention relates generally to improved semiconductorimaging devices and in particular to a silicon imaging device having amulti-layered gate and a second gate which overlaps the multi-layeredgate, and that can be fabricated using a standard CMOS process.

BACKGROUND OF THE INVENTION

[0002] There are a number of different types of semiconductor-basedimagers, including charge coupled devices (CCDs), photodiode arrays,charge injection devices and hybrid focal plane arrays. CCD technologyis often employed for image acquisition and enjoys a number ofadvantages which makes it the incumbent technology, particularly forsmall size imaging applications. CCDs are capable of large formats withsmall pixel size and they employ low noise charge domain processingtechniques.

[0003] However, CCD imagers also suffer from a number of disadvantages.For example, they are susceptible to radiation damage, they exhibitdestructive read-out over time, they require good light shielding toavoid image smear and they have a high power dissipation for largearrays. Additionally, while offering high performance, CCD arrays aredifficult to integrate with CMOS processing in part due to a differentprocessing technology and to their high capacitances, complicating theintegration of on-chip drive and signal processing electronics with theCCD array. While there have been some attempts to integrate on-chipsignal processing with CCD arrays, these attempts have not been entirelysuccessful. CCDs also must transfer an image by line charge transfersfrom pixel to pixel, requiring that the entire array be read out into amemory before individual pixels or groups of pixels can be accessed andprocessed. This takes time. CCDs may also suffer from incomplete chargetransfer from pixel to pixel which results in image smear.

[0004] Because of the inherent limitations in CCD technology, there isan interest in CMOS imagers for possible use as low cost imagingdevices. A filly compatible CMOS sensor technology enabling a higherlevel of integration of an image array with associated processingcircuits would be beneficial to many digital applications such as, forexample, in cameras, scanners, machine vision systems, vehiclenavigation systems, video telephones, computer input devices,surveillance systems, auto focus systems, star trackers, motiondetection systems, image stabilization systems and data compressionsystems for high-definition television.

[0005] The advantages of CMOS imagers over CCD imagers are that CMOSimagers have a low voltage operation and low power consumption; CMOSimagers are compatible with integrated on-chip electronics (controllogic and timing, image processing, and signal conditioning such as A/Dconversion); CMOS imagers allow random access to the image data; andCMOS imagers have lower fabrication costs as compared with theconventional CCD because standard CMOS processing techniques can beused. Additionally, low power consumption is achieved for CMOS imagersbecause only one row of pixels at a time needs to be active during thereadout and there is no charge transfer (and associated switching) frompixel to pixel during image acquisition. On-chip integration ofelectronics is particularly advantageous because of the potential toperform many signal conditioning functions in the digital domain (versusanalog signal processing) as well as to achieve a reduction in systemsize and cost.

[0006] A CMOS imager circuit includes a focal plane array of pixelcells, each one of the cells including either a photogate,photoconductor or a photodiode overlying a substrate for accumulatingphoto-generated charge in the underlying portion of the substrate. Areadout circuit is connected to each pixel cell and includes at least anoutput field effect transistor formed in the substrate and a chargetransfer section formed on the substrate adjacent the photogate,photoconductor or photodiode having a sensing node, typically a floatingdiffusion node, connected to the gate of an output transistor. Theimager may include at least one electronic device such as a transistorfor transferring charge from the underlying portion of the substrate tothe floating diffusion node and one device, also typically a transistor,for resetting the node to a predetermined charge level prior to chargetransference.

[0007] In a CMOS imager, the active elements of a pixel cell perform thenecessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to the floatingdiffusion node accompanied by charge amplification; (4) resetting thefloating diffusion node to a known state before the transfer of chargeto it; (5) selection of a pixel for readout; and (6) output andamplification of a signal representing pixel charge. Photo charge may beamplified when it moves from the initial charge accumulation region tothe floating diffusion node. The charge at the floating diffusion nodeis typically converted to a pixel output voltage by a source followeroutput transistor. The photosensitive element of a CMOS imager pixel istypically either a depleted p-n junction photodiode or a field induceddepletion region beneath a photogate or photoconductor. For photodiodes,image lag can be eliminated by completely depleting the photodiode uponreadout.

[0008] CMOS imagers of the type discussed above are generally known asdiscussed, for example, in Nixon et al., “256×256 CMOS Active PixelSensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol.31(12), pp. 2046-2050 (1996); Mendis et al., “CMOS Active Pixel ImageSensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453(1994), as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515,which are herein incorporated by reference.

[0009] To provide context for the invention, an exemplary CMOS imagingcircuit is described below with reference to FIG. 1. The circuitdescribed below, for example, includes a photogate for accumulatingphoto-generated charge in an underlying portion of the substrate. Itshould be understood that the CMOS imager may include a photodiode orother image to charge converting device, in lieu of a photogate, as theinitial accumulator for photo-generated charge.

[0010] Reference is now made to FIG. 1 which shows a simplified circuitfor a pixel of an exemplary CMOS imager using a photogate and having apixel photodetector circuit 14 and a readout circuit 60. It should beunderstood that while FIG. 1 shows the circuitry for operation of asingle pixel, that in practical use there will be an M×N array of pixelsarranged in rows and columns with the pixels of the array accessed usingrow and column select circuitry, as described in more detail below.

[0011] The photodetector circuit 14 is shown in part as across-sectional view of a semiconductor substrate 16 typically a p-typesilicon, having a surface well of p-type material 20. An optional layer18 of p-type material may be used if desired, but is not required.Substrate 16 may be formed of, for example, Si, SiGe, Ge, or GaAs.Typically the entire substrate 16 is p-type doped silicon substrate andmay contain a surface p-well 20 (with layer 18 omitted), but many otheroptions are possible, such as, for example p on p− substrates, p on p+substrates, p-wells in n-type substrates or the like. The terms wafer orsubstrate used in the description includes any semiconductor-basedstructure having an exposed surface in which to form the circuitstructure used in the invention. Wafer and substrate are to beunderstood as including silicon-on-insulator (SOI) technology,silicon-on-sapphire (SOS) technology, doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. Furthermore, whenreference is made to a wafer or substrate in the following description,previous process steps may have been utilized to form regions/junctionsin the base semiconductor structure or foundation.

[0012] An insulating layer 22 such as, for example, silicon dioxide isformed on the upper surface of p-well 20. The p-type layer may be ap-well formed in substrate 16. A photogate 24 thin enough to passradiant energy or of a material which passes radiant energy is formed onthe insulating layer 22. The photogate 24 receives an applied controlsignal PG which causes the initial accumulation of pixel charges in n+region 26. The n+ type region 26, adjacent one side of photogate 24, isformed in the upper surface of p-well 20. A transfer gate 28 is formedon insulating layer 22 between n+ type region 26 and a second n+ typeregion 30 formed in p-well 20. The n+ regions 26 and 30 and transfergate 28 form a charge transfer transistor 29 which is controlled by atransfer signal TX. The n+ region 30 is typically called a floatingdiffusion region. It is also a node for passing charge accumulatedthereat to the gate of a source follower transistor 36 described below.

[0013] A reset gate 32 is also formed on insulating layer 22 adjacentand between n+ type region 30 and another n+ region 34 which is alsoformed in p-well 20. The reset gate 32 and n+ regions 30 and 34 form areset transistor 31 which is controlled by a reset signal RST. The n+type region 34 is coupled to voltage source V_(DD), e.g., 5 volts. Thetransfer and reset transistors 29, 31 are n-channel transistors asdescribed in this implementation of a CMOS imager circuit in a p-well.It should be understood that it is possible to implement a CMOS imagerin an n-well in which case each of the transistors would be p-channeltransistors. It should also be noted that while FIG. 1 shows the use ofa transfer gate 28 and associated transistor 29, this structure providesadvantages, but is not required.

[0014] Photodetector circuit 14 also includes two additional n-channeltransistors, source follower transistor 36 and row select transistor 38.Transistors 36, 38 are coupled in series, source to drain, with thesource of transistor 36 also coupled over lead 40 to voltage sourceV_(DD) and the drain of transistor 38 coupled to a lead 42. The drain ofrow select transistor 38 is connected via conductor 42 to the drains ofsimilar row select transistors for other pixels in a given pixel row. Aload transistor 39 is also coupled between the drain of transistor 38and a voltage source V_(SS), e.g. 0 volts. Transistor 39 is kept on by asignal V_(LN) applied to its gate.

[0015] The imager includes a readout circuit 60 which includes a signalsample and hold (S/H) circuit including a S/H n-channel field effecttransistor 62 and a signal storage capacitor 64 connected to the sourcefollower transistor 36 through row transistor 38. The other side of thecapacitor 64 is connected to a source voltage V_(SS). The upper side ofthe capacitor 64 is also connected to the gate of a p-channel outputtransistor 66. The drain of the output transistor 66 is connectedthrough a column select transistor 68 to a signal sample output nodeV_(OUTS) and through a load transistor 70 to the voltage supply V_(DD).A signal called “signal sample and hold” (SHS) briefly turns on the S/Htransistor 62 after the charge accumulated beneath the photogateelectrode 24 has been transferred to the floating diffusion node 30 andfrom there to the source follower transistor 36 and through row selecttransistor 38 to line 42, so that the capacitor 64 stores a voltagerepresenting the amount of charge previously accumulated beneath thephotogate electrode 24.

[0016] The readout circuit 60 also includes a reset sample and hold(S/H) circuit including a S/H transistor 72 and a signal storagecapacitor 74 connected through the S/H transistor 72 and through the rowselect transistor 38 to the source of the source follower transistor 36.The other side of the capacitor 74 is connected to the source voltageV_(SS). The upper side of the capacitor 74 is also connected to the gateof a p-channel output transistor 76. The drain of the output transistor76 is connected through a p-channel column select transistor 78 to areset sample output node V_(OUTR) and through a load transistor 80 tothe supply voltage V_(DD). A signal called “reset sample and hold” (SHR)briefly turns on the S/H transistor 72 immediately after the resetsignal RST has caused reset transistor 31 to turn on and reset thepotential of the floating diffusion node 30, so that the capacitor 74stores the voltage to which the floating diffusion node 30 has beenreset.

[0017] The readout circuit 60 provides correlated sampling of thepotential of the floating diffusion node 30, first of the reset chargeapplied to node 30 by reset transistor 31 and then of the stored chargefrom the photogate 24. The two samplings of the diffusion node 30charges produce respective output voltages V_(OUTR) and V_(OUTS) of thereadout circuit 60. These voltages are then subtracted(V_(OUTS)−V_(OUTR)) by subtractor 82 to provide an output signalterminal 81 which is an image signal independent of pixel to pixelvariations caused by fabrication variations in the reset voltagetransistor 31 which might cause pixel to pixel variations in the outputsignal.

[0018]FIG. 2 illustrates a block diagram for a CMOS imager having apixel array 200 with each pixel cell being constructed in the mannershown by element 14 of FIG. 1. FIG. 4 shows a 2×2 portion of pixel array200. Pixel array 200 comprises a plurality of pixels arranged in apredetermined number of columns and rows. The pixels of each row inarray 200 are all turned on at the same time by a row select line, e.g.,line 86, and the pixels of each column are selectively output by acolumn select line, e.g., line 42. A plurality of rows and column linesare provided for the entire array 200. The row lines are selectivelyactivated by the row driver 210 in response to row address decoder 220and the column select lines are selectively activated by the columndriver 260 in response to column address decoder 270. Thus, a row andcolumn address is provided for each pixel. The CMOS imager is operatedby the control circuit 250 which controls address decoders 220, 270 forselecting the appropriate row and column lines for pixel readout, androw and column driver circuitry 210, 260 which apply driving voltage tothe drive transistors of the selected row and column lines.

[0019]FIG. 3 shows a simplified timing diagram for the signals used totransfer charge out of photodetector circuit 14 of the FIG. 1 CMOSimager. The photogate signal PG is nominally set to 5V and pulsed from5V to 0V during integration. The reset signal RST is nominally set at2.5V. As can be seen from the figure, the process is begun at time t₀ bybriefly pulsing reset voltage RST to 5V. The RST voltage, which isapplied to the gate 32 of reset transistor 31, causes transistor 31 toturn on and the floating diffusion node 30 to charge to the V_(DD)voltage present at n+ region 34 (less the voltage drop V_(TH) oftransistor 31). This resets the floating diffusion node 30 to apredetermined voltage (V_(DD)−V_(TH)). The charge on floating diffusionnode 30 is applied to the gate of the source follower transistor 36 tocontrol the current passing through transistor 38, which has been turnedon by a row select (ROW) signal, and load transistor 39. This current istranslated into a voltage on line 42 which is next sampled by providinga SHR signal to the S/H transistor 72 which charges capacitor 74 withthe source follower transistor output voltage on line 42 representingthe reset charge present at floating diffusion node 30. The PG signal isnext pulsed to 0 volts, causing charge to be collected in n+ region 26.

[0020] A transfer gate voltage TX, similar to the reset pulse RST, isthen applied to transfer gate 28 of transistor 29 to cause the charge inn+ region 26 to transfer to floating diffusion node 30. It should beunderstood that for the case of a photogate, the transfer gate voltageTX may be pulsed or held to a fixed DC potential. For the implementationof a photodiode with a transfer gate, the transfer gate voltage TX mustbe pulsed. The new output voltage on line 42 generated by sourcefollower transistor 36 current is then sampled onto capacitor 64 byenabling the sample and hold switch 62 by signal SHS. The column selectsignal is next applied to transistors 68 and 70 and the respectivecharges stored in capacitors 64 and 74 are subtracted in subtractor 82to provide a pixel output signal at terminal 81. It should also be notedthat CMOS imagers may dispense with the transfer gate 28 and associatedtransistor 29, or retain these structures while biasing the transfertransistor 29 to an always “on” state.

[0021] The operation of the charge collection of the CMOS imager isknown in the art and is described in several publications such as Mendiset al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172,pp. 19-29 (1994); Mendis et al., “CMOS Active Pixel Image Sensors forHighly Integrated Imaging Systems,” IEEE Journal of Solid StateCircuits, Vol. 32(2) (1997); and Eric R Fossum, “CMOS Image Sensors:Electronic Camera on a Chip,” IEDM Vol. 95, pp. 17-25 (1995) as well asother publications. These references are incorporated herein byreference.

[0022] The pixel cell 14 shown in FIG. 1 contains a transfer transistor29 having a gate stack 28, a source n+ region 26 and a drain floatingdiffusion region 30. Because the transfer gate stack 28 is separatedfrom the photogate 24 by a relatively wide gap, e.g., 0.25 microns, thepresence of a coupling region 26 is necessary to electrically couple thephotogate 24 to the transfer gate stack 28. When a signal TX is appliedto the transfer gate stack 28, the coupling region 26 functions as aconducting channel to pass charges from the doped layer 27 under thephotogate into the channel region of the transfer transistor 29, andthen to the floating diffusion region 30. Although this pixel cell 14 issimple to fabricate because it is a single polysilicon process, i.e., ituses a single layer of polysilicon as the gate layer in the photogate24, transfer gate 28 and reset gate 32, it has the disadvantages ofadded noise and incomplete charge transfer as a result of having toincorporate the diffused region 26.

[0023] To overcome these disadvantages, double polysilicon structureshave been developed in which the photogate 24 and reset gate 32 areformed using the same layer of polysilicon. After spacer formation thetop surface of all polysilicon gates are then oxidized, and then atransfer gate 28 is formed from a second layer of polysilicon thatoverlaps the photogate 24 to some degree. The overlapping of thephotogate 24 and the transfer gate 28 with only a thin, e.g., less than100 nm, layer of spacer insulator between them permits electricalcoupling to occur between the doped layer 27 underlying the photogate 24and the floating diffusion region 30. No coupling region 26 is requiredfor this pixel cell 14. Although this pixel cell 14 provides improvedcontrol over the potential stored in the 100 nm overlapping regionbetween the edge of the photogate 24 and the transfer gate 28, andresults in increased charge transfer from the doped layer 27 to thefloating diffusion region 30, there are significant processingdifficulties in the fabrication methods used to create the pixel cell14. The oxidation of the photogate stack 24 prior to transfer gate stack28 formation results in asperities, points, and other defects in theoxide layer insulating the transfer gate polysilicon from the photogatepolysilicon, resulting in low breakdown of the insulating gate oxidebetween these two overlying polysilicons, improper electricalfunctioning, and poor processing yield. Additionally, this oxidation ofthe first polysilicon layer, prior to the deposition of the secondpolysilicon layer which will form the transfer gate 28, forms the secondgate oxide under the transfer gate. As geometries have shrunk to improveperformance and yield, the gate oxide must be grown thinner to maintainlow threshold voltages and maintain performance at the shortergeometries. So the thinning of the second gate oxide continues to causea degradation in the breakdown voltage between these two overlappingpolysilicon layers.

[0024] This process also suffers from the alignment required to do themasked implant of the n-doped region 27, requiring careful alignment sothat the doped region 27 does not extend across the transfer gate 28which will be formed in later processing. In order to achieve this thetransfer gate 28 is made larger to account for implant misalignmenterrors. This process also suffers from the fact that all transistorsformed by the first polysilicon deposition including the photogate 24and reset gate 32 cannot be silicided gates, which would improve circuitspeed and performance, because of two reasons: (1) the top silicidecannot be oxidized to provide a reliable insulating oxide between thephotogate 24 and the transfer gate 28 and (2) a silicide layer on top ofthe photogate would block signal light from passing through thephotogate into the signal storage region 27 below the photogate.

[0025] There is needed, therefore, an improved multi-layered gatestructure formed with an overlapping second gate so that a doped regionis not required to transfer charge between the two gates. Also needed isa multi-layered transfer gate 28 and an overlapping photogate 24, or amulti-layered photogate 24 with an overlapping transfer gate 28 so thata n-doped region 26 is not required. A method of fabricating amulti-layered gate that solves the reduced process yield associated withthe low photogate polysilicon to transfer polysilicon breakdown voltageis needed. It would also be advantageous if this new method would alsoprovide silicided gates for improved speed and circuit performance whilesimultaneously allowing signal light to pass through the photogate.

SUMMARY OF THE INVENTION

[0026] The present invention provides a multi-layered gate stack processfor use in fabricating a pixel sensor cell. The multi-layered gates havemultiple layers including a conductive layer, an optional silicidelayer, and an insulating layer, all of which are patterned and etchedsimultaneously over a first insulating layer. Also provided are methodsfor forming the multi-layered gates of the present invention, and aprocess that achieves high yield overlap process for aphotogate-transfer gate overlap that does not require the n-doped region26. The combination of a multi-layered gate and an overlapping gate maybe a multi-layered transfer gate with an overlapping photogate, amulti-layered photogate with an overlapping transfer gate, amulti-layered source follower gate with an overlapping row select gate,a multi-layered row select gate with an overlapping source followergate, or any other suitable combination.

[0027] Additional advantages and features of the present invention willbe apparent from the following detailed description and drawings whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a representative circuit of a CMOS imager.

[0029]FIG. 2 is a block diagram of a CMOS pixel sensor chip.

[0030]FIG. 3 is a representative timing diagram for the CMOS imager.

[0031]FIG. 4 is a representative pixel layout showing a 2×2 pixellayout.

[0032]FIG. 5 is a cross-sectional view of a pixel sensor cell accordingto one embodiment of the present invention.

[0033]FIG. 6 is a cross-sectional view of a pixel sensor cell accordingto a second embodiment of the present invention.

[0034]FIG. 7 is a cross-sectional view of a pixel sensor cell accordingto a third embodiment of the present invention.

[0035]FIG. 8 is a cross-sectional view of a pixel sensor cell accordingto a fourth embodiment of the present invention.

[0036]FIG. 9 is a cross-sectional view of a semiconductor waferundergoing the process of a preferred embodiment of the invention.

[0037]FIG. 10 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 9.

[0038]FIG. 11 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 10.

[0039]FIG. 12 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 11.

[0040]FIG. 13 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 12.

[0041]FIG. 14 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 13.

[0042]FIG. 15 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 14.

[0043]FIG. 16 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 15.

[0044]FIG. 17 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 16.

[0045]FIG. 18 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 17.

[0046]FIG. 19 is an illustration of a computer system having a CMOSimager according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0047] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0048] The terms “wafer” and “substrate” are to be understood asincluding silicon-on-insulator (SOI) or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in the basesemiconductor structure or foundation. In addition, the semiconductorneed not be silicon-based, but could be based on silicon-germanium,germanium, or gallium arsenide.

[0049] The term “pixel” refers to a picture element unit cell containinga photosensor and transistors for converting electromagnetic radiationto an electrical signal. For purposes of illustration, a representativepixel is illustrated in the figures and description herein, andtypically fabrication of all pixels in an imager will proceedsimultaneously in a similar fashion. The following detailed descriptionis, therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims.

[0050] The structure of the pixel cell 14 of the first embodiment isshown in more detail in FIG. 5. The pixel cell 14 may be formed in asubstrate 16 having a doped layer or well 20 of a first conductivitytype, which for exemplary purposes is treated as a p-type substrate.Three gate stacks are formed in the pixel cell 14 as shown: amulti-layered transfer gate stack 28, a multi-layered reset transistorgate stack 32 of the reset transistor 31, and a semitransparentphotogate conductor 24 formed partially over the multi-layered transfergate stack 28. In between the reset transistor gate 32 and the transfergate 28 is a doped region 30 that is the source for the reset transistor31, and on the other side of the reset transistor gate 32 is a dopedregion 34 that acts as a drain for the reset transistor. The dopedregions 30, 34 are doped to a second conductivity type, which forexemplary purposes is treated as n-type. The first doped region 30 isthe floating diffusion region, sometimes also referred to as a floatingdiffusion node, and the second doped region 34 is connected to voltagesource Vdd.

[0051] The multi-layered transfer gate stack 28 and the multi-layeredreset gate stack 32 include a first insulating layer 100 of grown ordeposited silicon oxide on the doped layer 20, and a conductive layer102, such as doped polysilicon or other suitable material, over thefirst insulating layer 100. A second insulating layer 108 of, forexample, silicon oxide (silicon dioxide), nitride (silicon nitride),oxynitride (silicon oxynitride), ON (oxide-nitride), NO (nitride-oxide),or ONO (oxide-nitride-oxide) may be formed, if desired; also a silicidelayer 106 may be formed in the multi-layered gate stacks 28, 32, betweenthe conductive layer 102 and the second insulating layer 108, ifdesired. Advantageously, all other transistors in the imager circuitdesign, except for the photogate, may have this additionally formedsilicide layer, thus improving gate delay and increasing circuit speed.This silicide layer may be titanium silicide, tungsten silicide, cobaltsilicide, molybdenum silicide, or tantalum silicide. Layer 106 couldalso be a barrier layer/refractory metal such as TiN/W or WN_(X)/W or itcould be entirely formed of WN_(X). The implanted n-doped region 27 isself-aligned to the transfer gate edge and forms a photosensitive chargestorage region for collecting photogenerated electrons. Insulatingsidewalls 110 of, for example, silicon dioxide, silicon nitride, siliconoxynitride, ON, NO, or ONO are also formed on the sides of the gatestacks 28, 32. The photogate stack 24 includes a first insulating layer114 formed over the n-doped layer 27, and a conductive layer 103 ofdoped polysilicon, tin oxide, indium tin oxide, or other suitablesemitransparent conductive material over the first insulating layer 114.

[0052] The so-formed photogate 24 is isolated from the multi-layeredtransfer gate stack 28 by the combination of the spacers 110 and thesecond insulating layer 108. These layers can be made relatively thickwithout sacrificing imager or circuit performance and thus achieve goodisolation between the photogate and the transfer gate, high breakdownvoltages, and high yield. This new processing method does not depend onthe non-uniform growth of an oxide on a polysilicon layer to provideisolation between two gates.

[0053] Because the transfer gate stack 28 has a second insulating layer108, and the conductive 106 and silicide 108 layers of the transfer gatestack 28 are isolated on the sides by sidewall spacers 110, there isso-formed a uniformly thick isolation free of asperities and points thatenables high breakdown voltages and high yield. The relative thicknessand smoothness of the isolating insulators 108, 110 enables theformation thereon of a substantially defect-free gate layer 103 of thephotogate 24. Because the structural quality of the insulating layers108, 110 and the gate layer 103 is improved over structures known in theart, there are fewer electrical defects in photogate to transfer gateisolation of the present invention, and processing yields are improved.Also note that the edge of the photogate conductive layer 103 isself-aligned to the edge of the transfer gate 28 so that no interveningdoped region 26 is required as has been the case with past singlepolysilicon processes. In the case of FIG. 5, the first gate oxide 100is grown just before depositing the first conductive layer 102 and thesecond gate oxide 114 is grown just before depositing a secondconductive layer 103 which is, in the case of FIG. 5, a semitransparentlayer that forms the photogate.

[0054] As light radiation 12 in the form of photons passes through thesemitransparent photogate 24, electron-hole pairs are created in theunderlying silicon substrate and electrical carriers are stored in thedoped layer 27 underneath the photogate 24. The carriers may be eitherelectrons or holes, depending on the types of devices used in the pixelsensor cell 14. In the exemplary pixel cell 14 having n-channel devicesformed in a p-type doped layer 20, the stored carriers are electrons.When a signal TX is applied to the conductive layer 106 of the transfergate stack 28, the transfer gate is turned on and electrical couplingoccurs due to the narrow gap between the photogate 24 and the transfergate stack 28, and the coupling capacitance and electrical fringingfields between these two devices, and carriers are transferred from thedoped layer 27 under the photogate into the floating diffusion region30.

[0055] A multi-layered photogate 24 with an overlapping transfer gate28, as shown in FIG. 6, works in essentially the same fashion as isdescribed above for the multi-layered transfer gate 28 with anoverlapping photogate 24. The design of the gates is varied as necessaryto achieve proper electrical functioning of the device, for example, themulti-layered photogate 24 of FIG. 6 would not have the optionalsilicide layer 106. On the other hand, the overlapping transfer gate inFIG. 6 could have a silicide or barrier metal/refractory metal layerover the polysilicon layer 103. Similar to FIG. 5, the first gate oxide100 is grown just before depositing the first conductive layer 102, andthe second gate oxide 114 is grown just before depositing the secondconductive layer 103 which is, in the case of FIG. 6, the transfer gate.

[0056] Other gates in the pixel cell may be formed to overlap, as isshown in FIGS. 7 and 8, which depict, respectively, a multi-layered rowselect gate 38 with an overlapping source follower gate 36, and amulti-layered source follower gate 36 with an overlapping row selectgate 38. Charge on the floating diffusion region 30 is connected to thesource follower gate 36 via lead 44. This charge regulates the degree towhich the source follower transistor is turned on. If the row selectgate 38 is also turned on by signal ROW, then current flows betweensource region 120 and drain region 122, and via lead 42 to signalprocessing circuitry located outside the pixel array. In these twoapplications the overlapping gate may have a silicide orbarrier/refractory metal layer over the polysilicon layer 103 and mayalso have an overlapping insulating-layer.

[0057] The multi-layered transfer gate 28 is manufactured through aprocess described as follows, and illustrated by FIGS. 9 through 18.Referring now to FIG. 9, a substrate 16, which may be any of the typesof substrates described above, is doped to form a doped substrate layeror well 20 of a first conductivity type, which for exemplary purposeswill be described as p-type. The process sequence described andillustrated below provides for the formation of n-channel devices in ap-type substrate. It follows that the invention may also be carried outby forming p-channel devices in an n-type substrate by substitution ofthe appropriately doped materials and addition of appropriate masks.Also, p-channel and n-channel devices may be formed in the samesubstrate.

[0058] For exemplary purposes, the fabrication of a multi-layeredtransfer gate with an overlapping photogate is described and illustratedherein, but the process of the present invention is not limited thereto.Fabrication of the other embodiments of the present invention such as amulti-layered row select gate with an overlapping source follower gatewould proceed substantially as described below.

[0059] The processing is shown in FIG. 9 after the field oxide isolationis completed. Field isolation is used to isolate doped or conductiveregions to be later formed in the silicon substrate. Field oxidation bythe LOCOS process which involves a thermal oxidation of the silicon isshown. However, it is well known to those skilled in the art that onemay substitute a shallow trench isolation (STI) process which involvesthe deposition of an oxide into trenches etched into the silicon.

[0060] As shown in FIG. 10, the next step is to form a first insulatinglayer 100 of silicon oxide, silicon nitride, silicon oxynitride, ON, NO,or ONO, on the top of the doped layer 20 by suitable means such asgrowth by thermal oxidation of the doped layer 20, or by deposition.Next, as shown in FIG. 11, a first conductive layer 102 is formed, bychemical vapor deposition (CVD), or other suitable means, on top of thefirst insulating layer 100. The first conductive layer 102 may be dopedpolysilicon and is preferably about 10 to 500 nm thick.

[0061] Referring now to FIGS. 12 and 13, the next step in the process isthe formation of a silicide layer, if desired. In one embodiment, ametal layer 104 is formed on top of the first conductive layer 102 bysuitable means such as CVD, evaporation, or sputtering. Next, a silicidelayer 106 is formed by annealing the metal layer 104 at a temperaturewithin the approximate range of 300 to 900 degrees Celsius. A secondembodiment is to deposit the silicide layer 106 directly onto the firstconductive layer 102 by CVD or other suitable means. The metal silicidemay be any suitable metal silicide such as the silicides of tungsten,titanium, molybdenum, tantalum, platinum, palladium, iridium or cobalt.In a third embodiment the metal layer could be a deposited barriermetal/metal conductor layer combination such as TiN/W, WN_(X)/W, or anyother suitable barrier metal/metal conductor combination such as WN_(X)alone, and it may be deposited by CVD, evaporation, or sputtering.

[0062]FIG. 14 depicts the next step in the process, in which a secondinsulating layer 108 is formed on the silicide layer 106 by CVD, orother suitable, means. The second insulating layer may be formed fromany suitable material such as silicon oxide, silicon nitride, ONO, ON,or NO. It is to be understood that the oxide layers could also be asilicum rich oxide layer commonly used as an inorganic ARC layer(anti-reflection coating), which additionally improves photo patterning.

[0063] Referring now to FIG. 15, the next step is to define gate stacks.A resist (not shown) and mask (not shown) are applied, andphotolithographic techniques are used to define the areas which will begate stacks across the wafer. A suitable removal process such as RIE orother directional etching is used to remove the second insulating layer108, the silicide layer 106, and the first conductive layer 102 to leavea transfer gate stack 28, a reset transistor gate stack 32, and thefirst insulating layer 100 on the surface of the wafer. Alternatively,the first insulating layer 100 may also be partially removed from thesurface of the wafer in the regions exposed to the etch. Othertransistors in the imaging pixel such as the source follower transistorand the row select transistor are similarly formed though not shown atthis time. Also any peripheral logic transistors can be advantageouslyso formed at this point in the processing.

[0064] Next, as shown in FIG. 16, spacers or sidewalls 110 are formed onthe sides of the gate stacks 28, 32. The sidewalls 110 may be formed ofdeposited insulation materials such as silicon oxide, silicon nitride,silicon oxynitride, or ONO or ON or NO. After deposition of theinsulating material it is etched using an anisotropic dry etch thatforms the sidewall spacers. This anisotropic etch may partially orcompletely remove the remaining first insulating layer 100. FIG. 16shows the gate oxide 100 to be completely removed by the spacer overetchin the regions where the gate oxide is not protected by the overlappinggate stack.

[0065] As shown in FIG. 17, after the spacers are formed, the maskedsource-drain implant 34, the masked floating diffusion implant 30, andthe self-aligned masked photogate implant 27 are performed. For the caseof n-channel devices in a p-well 20, these are all n-type implants suchas arsenic, antimony, or phosphorus. It is possible with some sacrificein performance to save costs by implanting these regions with just oneor two masks rather than the three indicated herein. The implantsdiffuse under subsequent thermal treatment. In FIG. 17 we show thesediffused, implanted regions after those thermal steps have occurred.There will be other masked implantations to improve transistorperformance, set Vt's, etc., which for sake of simplicity, are notshown.

[0066] As shown in FIG. 18, the next step is to form the photogate 24. Asecond insulating layer 114 is formed or reformed on the siliconsubstrate by suitable means such as growth by thermal oxidation. Next, asecond conductive layer 103 is deposited, by CVD, or other suitablemeans, on top of the second insulating layer 114. The second conductivelayer 103 may be doped polysilicon or other suitable semitransparentconductive material such as tin oxide or indium tin oxide, and ispreferably about 10 to 500 nm thick. A resist (not shown) and mask (notshown) are applied to selectively pattern an area where the photogate 24is to be formed. The photogate is then etched by suitable wet or dryetching methods, preferably by an anisotropic dry etch. FIG. 18 show thereset, transfer, and photogates in the imager after the photogate hasbeen patterned, etched and the resist patterning layers removed.

[0067] The multi-layered gate process with overlapping gates isessentially complete at this stage, and conventional processing methodsmay then be used to form contacts and wiring to connect gate lines andother connections in the pixel cell 14. For example, the entire surfacemay then be covered with a passivation layer of, e.g., silicon dioxide,BSG, PSG, or BPSG, which is CMP planarized and etched to provide contactholes, which are then metallized to provide contacts to the photogate,reset gate, and transfer gate. Conventional multiple layers ofconductors and insulators may also be used to interconnect thestructures in the manner shown in FIG. 1. Pixel arrays having thetransfer gates of the present invention, and described with reference toFIGS. 5-18, may be further processed as known in the art to arrive atCMOS imagers having the functions and features of those discussed withreference to FIGS. 1-4.

[0068] A typical processor based system which includes a CMOS imagerdevice according to the present invention is illustrated generally at400 in FIG. 19. A processor based system is exemplary of a system havingdigital circuits which could include CMOS imager devices. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision system, vehicle navigation system, videotelephone, surveillance system, auto focus system, star tracker system,motion detection system, image stabilization system and data compressionsystem for high-definition television, all of which can utilize thepresent invention.

[0069] A processor system, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 444, e.g., amicroprocessor, that communicates with an input/output (I/O) device 446over a bus 452. The CMOS imager 442 also communicates with the systemover bus 452. The computer system 400 also includes random access memory(RAM) 448, and, in the case of a computer system may include peripheraldevices such as a floppy disk drive 454 and a compact disk (CD) ROMdrive 456 which also communicate with CPU 444 over the bus 452. CMOSimager 442 is preferably constructed as an integrated circuit whichincludes pixels containing a multi-layered gate, as previously describedwith respect to FIGS. 5 through 18. The CMOS imager 442 may be combinedwith a processor, such as a CPU, digital signal processor ormicroprocessor, with or without memory storage, in a single integratedcircuit, or may be on a different chip than the processor.

[0070] As can be seen by the embodiments described herein, the presentinvention encompasses multi-layered gates in a pixel sensor cell thatare at least partially overlapped by an adjacent gate. The multi-layeredgate is a complete gate stack and exhibits improved insulation from theoverlapping gate, thereby resulting in fewer shorts between the twogates. The process embodiments described herein enable formation of amulti-layered gate with improved yield and reliability.

[0071] It should again be noted that although the invention has beendescribed with specific reference to CMOS imaging circuits having aphotogate and a floating diffusion region, the invention has broaderapplicability and may be used in any CMOS or CCD imaging apparatus whereoverlapping gates are required or advantageous. Similarly, the processdescribed above is but one method of many that could be used. The abovedescription and drawings illustrate preferred embodiments which achievethe objects, features and advantages of the present invention. It is notintended that the present invention be limited to the illustratedembodiments. Any modification of the present invention which comeswithin the spirit and scope of the following claims should be consideredpart of the present invention.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A pixel sensor cell for use in an imagingdevice, said pixel sensor cell comprising: a first insulating layerformed on a substrate; a first gate formed on said first insulatinglayer, said first gate comprising a first conductive layer on said firstinsulating layer, a second insulating layer on the first conductivelayer, and insulating spacers formed on the sides of said first gate;and a second gate formed on said first insulating layer, said secondgate comprising a second conductive layer formed on said firstinsulating layer and extending at least partially over said first gate.2. The pixel sensor cell of claim 1, wherein the first insulating layeris a layer of material selected from the group consisting of siliconoxide, silicon nitride, silicon oxynitride, ON, NO, and ONO.
 3. Thepixel sensor cell of claim 1, wherein the first conductive layer is alayer of doped polysilicon.
 4. The pixel sensor cell of claim 1, whereinsaid first gate further comprises a barrier metal layer on the firstconductive layer.
 5. The pixel sensor cell of claim 4, wherein thebarrier metal is titanium nitride.
 6. The pixel sensor cell of claim 4,wherein the barrier metal is tungsten nitride.
 7. The pixel sensor cellof claim 4, wherein said first gate further comprises a tungsten layeron the barrier metal layer.
 8. The pixel sensor cell of claim 1, whereinsaid first gate further comprises a silicide layer on the firstconductive layer.
 9. The pixel sensor cell of claim 8, wherein thesilicide layer is a layer of metal silicide selected from the groupconsisting of titanium silicide, tungsten silicide, molybdenum silicide,tantalum silicide, platinum silicide, palladium silicide, iridiumsilicide, and cobalt silicide.
 10. The pixel sensor cell of claim 1,wherein the second insulating layer is a deposited silicon oxide layer.11. The pixel sensor cell of claim 1, wherein the second insulatinglayer material is silicon nitride.
 12. The pixel sensor cell of claim 1,wherein the second insulating layer is ON.
 13. The pixel sensor cell ofclaim 1, wherein the second insulating layer is NO.
 14. The pixel sensorcell of claim 1, wherein the second insulating material is ONO.
 15. Thepixel sensor cell of claim 1, wherein the insulating spacers are siliconoxide spacers.
 16. The pixel sensor cell of claim 1, wherein theinsulating spacers are silicon nitride spacers.
 17. The pixel sensorcell of claim 1, wherein the insulating spacers are silicon oxynitridespacers.
 18. The pixel sensor cell of claim 1, wherein the insulatingspacers are ON spacers.
 19. The pixel sensor cell of claim 1, whereinthe insulating spacers are NO spacers.
 20. The pixel sensor cell ofclaim 1, wherein the insulating spacers are ONO spacers.
 21. The pixelsensor cell of claim 1, wherein the second conductive layer is a layerof doped polysilicon.
 22. The pixel sensor cell of claim 1, wherein thesecond conductive layer is a layer of semitransparent conductivematerial.
 23. The pixel sensor cell of claim 22, wherein thesemitransparent conductive material is tin oxide.
 24. The pixel sensorcell of claim 22, wherein the semitransparent conductive material isindium tin oxide.
 25. The pixel sensor of claim 22, wherein thesemitransparent conductive material is a layer of doped polysilicon. 26.The pixel sensor cell of claim 1, wherein said second gate furthercomprises a barrier metal layer on the second conductive layer.
 27. Thepixel sensor of claim 26, wherein the barrier metal is titanium nitride.28. The pixel sensor of claim 26, wherein the barrier metal is tungstennitride.
 29. The pixel sensor cell of claim 26 wherein said second gatefurther comprises a tungsten layer on the barrier metal layer.
 30. Thepixel sensor cell of claim 1, wherein said second gate further comprisesa silicide layer on the second conductive layer.
 31. The pixel sensorcell of claim 1, wherein the imaging device is a CMOS imager.
 32. Thepixel sensor cell of claim 1, wherein the imaging device is a CCDimager.
 33. The pixel sensor cell of claim 1, wherein said first gate isa source follower gate, and said second gate is a row select gate. 34.The pixel sensor cell of claim 1, wherein said first gate is a rowselect gate, and said second gate is a source follower gate.
 35. Thepixel sensor cell of claim 1, wherein said first gate is a transfer gateand said second gate is a photogate.
 36. The pixel sensor cell of claim1, wherein said first gate is a photogate and said second gate is atransfer gate.
 37. A pixel sensor cell for use in an imaging device,said pixel sensor cell comprising: a first insulating layer formed on asubstrate; a first gate formed on said first insulating layer, saidfirst gate comprising a first conductive layer on said first insulatinglayer, a second insulating layer on the first conductive layer, andinsulating spacers formed on the sides of said first gate; and a secondgate formed on said second insulating layer, said second gate comprisinga second conductive layer formed on said second insulating layer andextending at least partially over said first gate.
 38. The pixel sensorcell of claim 37, wherein the first insulating layer is a layer selectedfrom the group consisting of silicon oxide, silicon nitride, siliconoxynitride, ON, NO, and ONO.
 39. The pixel sensor cell of claim 37,wherein the first conductive layer is a layer of doped polysilicon. 40.The pixel sensor cell of claim 37, wherein said first gate furthercomprises a barrier metal layer on the first conductive layer.
 41. Thepixel sensor cell of claim 40, wherein the barrier metal is titaniumnitride.
 42. The pixel sensor cell of claim 40, wherein the barriermetal is tungsten nitride.
 43. The pixel sensor cell of claim 40,wherein said first gate further comprises a tungsten layer on thebarrier metal layer.
 44. The pixel sensor cell of claim 37, wherein saidfirst gate further comprises a silicide layer on the first conductivelayer.
 45. The pixel sensor cell of claim 44, wherein the silicide layeris a layer of metal silicide selected from the group consisting oftitanium silicide, tungsten silicide, molybdenum silicide, tantalumsilicide, platinum silicide, palladium silicide, iridium silicide, andcobalt silicide.
 46. The pixel sensor cell of claim 37, wherein thesecond insulating layer is a deposited silicon oxide layer.
 47. Thepixel sensor cell of claim 37, wherein the second insulating layermaterial is silicon nitride.
 48. The pixel sensor cell of claim 37,wherein the second insulating layer is ON.
 49. The pixel sensor cell ofclaim 37, wherein the second insulating layer is NO.
 50. The pixelsensor cell of claim 37, wherein the second insulating material is ONO.51. The pixel sensor cell of claim 37, wherein the insulating spacersare silicon oxide spacers.
 52. The pixel sensor cell of claim 37,wherein the insulating spacers are silicon nitride spacers.
 53. Thepixel sensor cell of claim 37, wherein the insulating spacers aresilicon oxynitride spacers.
 54. The pixel sensor cell of claim 37,wherein the insulating spacers are ON spacers.
 55. The pixel sensor cellof claim 37, wherein the insulating spacers are NO spacers.
 56. Thepixel sensor cell of claim 37, wherein the insulating spacers are ONOspacers.
 57. The pixel sensor cell of claim 37, wherein the secondconductive layer is a layer of doped polysilicon.
 58. The pixel sensorcell of claim 37, wherein the second conductive layer is a layer ofsemitransparent conductive material.
 59. The pixel sensor cell of claim58, wherein the semitransparent conductive material is tin oxide. 60.The pixel sensor cell of claim 58, wherein the semitransparentconductive material is indium tin oxide.
 61. The pixel sensor of claim58, wherein the semitransparent conductive material is a layer of dopedpolysilicon.
 62. The pixel sensor cell of claim 37, wherein said secondgate further comprises a barrier metal layer on the second conductivelayer.
 63. The pixel sensor of claim 62, wherein the barrier metal istitanium nitride.
 64. The pixel sensor of claim 62, wherein the barriermetal is tungsten nitride.
 65. The pixel sensor cell of claim 62 whereinsaid second gate further comprises a tungsten layer on the barrier metallayer.
 66. The pixel sensor cell of claim 37, wherein said second gatefurther comprises a silicide layer on the second conductive layer. 67.The pixel sensor cell of claim 37, wherein the imaging device is a CMOSimager.
 68. The pixel sensor cell of claim 37, wherein the imagingdevice is a CCD imager.
 69. The pixel sensor cell of claim 37, whereinsaid first gate is a source follower gate, and said second gate is a rowselect gate.
 70. The pixel sensor cell of claim 37, wherein said firstgate is a row select gate, and said second gate is a source followergate.
 71. The pixel sensor cell of claim 37, wherein said first gate isa transfer gate and said second gate is a photogate.
 72. The pixelsensor cell of claim 37, wherein said first gate is a photogate and saidsecond gate is a transfer gate.
 73. A pixel sensor cell for use in animaging device, said pixel sensor cell comprising: a photosensitiveregion of a first conductivity type formed in a substrate; a floatingdiffusion region of a second conductivity type formed in the substrateand spaced from said photosensitive region; a first insulating layerformed on the substrate; a first gate formed on said first insulatinglayer over said photosensitive region, said first gate comprising afirst conductive layer on said first insulating layer, a secondinsulating layer on the first conductive layer, and insulating spacersformed on the sides of said first gate; and a second gate formed on saidfirst insulating layer, said second gate comprising a semitransparentconductive layer formed on said first insulating layer and extending atleast partially over said first gate.
 74. The pixel sensor cell of claim73, wherein the first conductive layer is a layer of doped polysilicon.75. The pixel sensor cell of claim 73, wherein the first conductivelayer is a layer of semitransparent conductive material.
 76. The pixelsensor cell of claim 73, wherein the second insulating layer is a layerof silicon oxide.
 77. The pixel sensor cell of claim 73, wherein theinsulating spacers are spacers selected from the group consisting ofsilicon oxide spacers, silicon nitride spacers, silicon oxynitridespacers, ON spacers, NO spacers, and ONO spacers.
 78. The pixel sensorcell of claim 73, wherein the semitransparent conductive material isdoped polysilicon.
 79. The pixel sensor cell of claim 73, wherein thesemitransparent conductive material is tin oxide.
 80. The pixel sensorcell of claim 73, wherein the semitransparent conductive material isindium tin oxide.
 81. The pixel sensor cell of claim 73, wherein theimaging device is a CMOS imager.
 82. The pixel sensor cell of claim 73,wherein the imaging device is a CCD imager.
 83. The pixel sensor cell ofclaim 73, wherein said second gate further comprises a barrier metallayer on the semitransparent conductive layer.
 84. The pixel sensor cellof claim 83, wherein the barrier metal is titanium nitride.
 85. Thepixel sensor of claim 83, wherein the barrier metal is tungsten nitride.86. The pixel sensor cell of claim 83, wherein said second gate furthercomprises a tungsten layer on the barrier metal layer.
 87. The pixelsensor cell of claim 73, wherein said second gate further comprises asilicide layer on the semitransparent conductive layer.
 88. A pixelsensor cell for use in an imaging device, said pixel sensor cellcomprising: a photosensitive region of a first conductivity type formedin a substrate; a floating diffusion region of a second conductivitytype formed in the substrate and spaced from said photosensitive region;a first insulating layer formed on the substrate; a first gate formed onsaid first insulating layer over said photosensitive region, said firstgate comprising a first conductive layer on said first insulating layer,a second insulating layer on the first conductive layer, and insulatingspacers formed on the sides of said first gate; and a second gate formedon said second insulating layer, said second gate comprising asemitransparent conductive layer formed on said second insulating layerand extending at least partially over said first gate.
 89. The pixelsensor cell of claim 88, wherein the first conductive layer is a layerof doped polysilicon.
 90. The pixel sensor cell of claim 88, wherein thefirst conductive layer is a layer of semitransparent conductivematerial.
 91. The pixel sensor cell of claim 88, wherein the secondinsulating layer is a layer of silicon oxide.
 92. The pixel sensor cellof claim 88, wherein the insulating spacers are spacers selected fromthe group consisting of silicon oxide spacers, silicon nitride spacers,silicon oxynitride spacers, ON spacers, NO spacers, and ONO spacers. 93.The pixel sensor cell of claim 88, wherein the semitransparentconductive material is doped polysilicon.
 94. The pixel sensor cell ofclaim 88, wherein the semitransparent conductive material is tin oxide.95. The pixel sensor cell of claim 88, wherein the semitransparentconductive material is indium tin oxide.
 96. The pixel sensor cell ofclaim 88, wherein the imaging device is a CMOS imager.
 97. The pixelsensor cell of claim 88, wherein the imaging device is a CCD imager. 98.The pixel sensor cell of claim 88, wherein said second gate furthercomprises a barrier metal layer on the semitransparent conductive layer.99. The pixel sensor cell of claim 98, wherein the barrier metal istitanium nitride.
 100. The pixel sensor of claim 98, wherein the barriermetal is tungsten nitride.
 101. The pixel sensor cell of claim 98,wherein said second gate further comprises a tungsten layer on thebarrier metal layer.
 102. The pixel sensor cell of claim 88, whereinsaid second gate further comprises a silicide layer on thesemitransparent conductive layer.
 103. A CMOS imager comprising: anarray of pixel sensor cells, each pixel sensor cell having at least twogates, wherein one of said at least two gates is formed to overlap atleast partially on another of said at least two gates; and a circuitelectrically connected to receive and process output signals from saidarray.
 104. The CMOS imager of claim 103, wherein the photogate isformed to overlap at least partially on the transfer gate.
 105. The CMOSimager of claim 103, wherein the transfer gate is formed to overlap atleast partially on the photogate.
 106. The CMOS imager of claim 103,wherein the source follower gate is formed to overlap at least partiallyon the row select gate.
 107. The CMOS imager of claim 103, wherein therow select gate is formed to overlap at least partially on the sourcefollower gate.
 108. A CMOS imager comprising: an array of pixel sensorcells, wherein each pixel sensor cell has a first gate stack, a secondgate formed to overlap at least partially on the first gate stack, and afloating diffusion region; and a circuit electrically connected toreceive and process output signals from said array.
 109. The CMOS imagerof claim 108, wherein the first gate stacks comprise a first insulatinglayer, and a conductive layer on the first insulating layer.
 110. TheCMOS imager of claim 108, wherein the second gates comprise a secondinsulating layer, and a second conductive layer on the second insulatinglayer.
 111. The CMOS imager of claim 108, wherein the first gate is atransfer gate and the second gate is a photogate.
 112. The CMOS imagerof claim 108, wherein the first gate is a photogate and the second gateis a transfer gate.
 113. The CMOS image of claim 108, wherein the firstgate is a source follower gate, and the second gate is a row selectgate.
 114. The CMOS imager of claim 108, wherein the first gate is a rowselect gate, and the second gate is a source follower gate.
 115. TheCMOS imager of claim 108, wherein each pixel sensor cell furthercomprises a reset transistor for periodically resetting a charge levelof the floating diffusion region.
 116. The CMOS imager of claim 63,wherein each pixel sensor cell further comprises an output transistorhaving a gate electrically connected to the floating diffusion region.117. An imager comprising: a CMOS imager, said CMOS imager comprising anarray of pixel sensor cells formed in a photosensitive region on asubstrate, wherein each pixel sensor cell has at least two gates,wherein one of said at least two gates is formed to overlap at leastpartially on another of said at least two gates, and a circuit formed insaid substrate and electrically connected to the array for receiving andprocessing signals representing an image output by the array and forproviding output data representing said image; and a central processingunit for receiving and processing data representing said image.
 118. Theimager of claim 117, wherein said array, said circuit, and said centralprocessing unit are formed on a single substrate.
 119. The imager ofclaim 117, wherein said array and said circuit are formed on a firstsubstrate and said central processing unit is formed on a secondsubstrate.
 120. A method of forming a multi-layered gate for use in animaging device, comprising the steps of: forming a first insulatinglayer on a substrate; forming a first conductive layer over the firstinsulating layer; forming a second insulating layer over the firstconductive layer; forming a first gate from the first conductive layerand the second insulating layer; forming insulating spacers on the sidesof the first gate; and forming a second gate by forming a secondconductive layer on the first insulating layer and extending over thefirst gate.
 121. The method of claim 120, wherein before said step offorming a second gate, said method further comprises: forming an oxidelayer on the substrate, wherein the second gate is formed by forming asecond conductive layer on the oxide layer and extending over the firstgate.
 122. The method of claim 120, wherein said step of forming a firstinsulating layer comprises thermal oxidation.
 123. The method of claim120, wherein said step of forming a first insulating layer comprisesdeposition.
 124. The method of claim 120, wherein said step of forming afirst insulating layer comprises forming a silicon oxide layer andhardening the silicon oxide layer with a nitrogen treatment.
 125. Themethod of claim 120, wherein said step of forming a first conductivelayer comprises chemical vapor deposition.
 126. The method of claim 120,wherein said step of forming a first conductive layer is a physicalvapor deposition step.
 127. The method of claim 120, further comprisingforming a metal silicide layer on the first conductive layer prior tothe step of forming a first gate.
 128. The method of claim 127, whereinsaid step of forming a metal silicide layer comprises chemical vapordeposition.
 129. The method of claim 127, wherein said step of forming ametal silicide layer further comprises forming a metal layer on thefirst conductive layer, and annealing the metal layer.
 130. The methodof claim 129, wherein the metal layer is a material selected from thegroup consisting of titanium, tungsten, molybdenum, tantalum, platinum,palladium, iridium, and cobalt.
 131. The method of claim 129, whereinsaid step of forming a metal layer comprises chemical vapor deposition.132. The method of claim 129, wherein said step of forming a metal layercomprises evaporation.
 133. The method of claim 129, wherein said stepof forming a metal layer comprises sputtering.
 134. The method of claim129, wherein said annealing step is carried out at a temperature withinthe range of approximately 300 to 900 degrees Celsius.
 135. The methodof claim 127, wherein said metal silicide layer is a layer selected fromthe group consisting of tungsten silicide, titanium silicide, molybdenumsilicide, tantalum silicide, platinum silicide, palladium silicide,iridium silicide, and cobalt silicide.
 136. The method of claim 120,wherein said step of forming a second insulating layer comprisesdeposition.
 137. The method of claim 120, wherein said step of forming afirst gate comprises directional etching of the first conductive layerand the second insulating layer.
 138. The method of claim 137, whereinsaid directional etching is a reactive ion etch.
 139. The method ofclaim 120, wherein said step of forming a second conductive layercomprises chemical vapor deposition.
 140. The method of claim 120,wherein said step of forming a second gate comprises directional etchingof the second conductive layer.
 141. The method of claim 140, whereinsaid directional etching is a reactive ion etch.
 142. The method ofclaim 120, wherein the first insulating layer is a layer of materialselected from the group consisting of silicon oxide, silicon nitride,silicon oxynitride, ON, NO, and ONO.
 143. The method of claim 1206,wherein the first conductive layer is a layer of doped polysilicon. 144.The method of claim 120, wherein the second insulating layer is a layerof material selected from the group consisting of deposited siliconoxide, silicon nitride, NO, ON, and ONO.
 145. The method of claim 120,wherein the insulating spacers are spacers selected from the groupconsisting of silicon oxide spacers, silicon nitride spacers, siliconoxynitride spacers, ON spacers, NO spacers, and ONO spacers.
 146. Themethod of claim 120, wherein the second conductive layer is a layer ofmaterial selected from the group consisting of doped polysilicon, tinoxide, and indium tin oxide.
 147. A method of forming a multi-layeredgate for use in an imaging device, comprising the steps of: providing asemiconductor substrate having a photosensitive region of a firstconductivity type; forming a first insulating layer on the semiconductorsubstrate and over the photosensitive region; forming a first conductivelayer over the first insulating layer; forming a second insulating layerover the first conductive layer; patterning at least the firstconductive layer to form a first gate; forming an oxide layer over thesemiconductor substrate; forming a second conductive layer over theoxide layer and at least a portion of the first conductive layer;forming a second gate from the second conductive layer and the oxidelayer; and forming a floating diffusion region of a second conductivitytype in the substrate adjacent the first gate on a side of the firstgate opposite the second gate.
 148. The method of claim 147, wherein thefirst gate is a transfer gate, and the second gate is a photogate. 149.The method of claim 147, wherein the first gate is a photogate, and thesecond gate is a transfer gate.
 150. The method of claim 147, whereinthe first gate is a row select gate, and the second gate is a sourcefollower gate.
 151. The method of claim 147, wherein the first gate is asource follower gate, and the second gate is a row select gate.
 152. Themethod of claim 147, wherein the first conductivity type is p-type, andthe second conductivity type is n-type.
 153. The method of claim 147,wherein the first conductivity type is n-type, and the secondconductivity type is p-type.
 154. The method of claim 147, wherein saidstep of forming a first insulating layer comprises thermal oxidation.155. The method of claim 147, wherein said step of forming a firstinsulating layer comprises deposition.
 156. The method of claim 147,wherein said step of forming a second insulating layer comprisesdeposition.
 157. The method of claim 147, wherein said step of forming afirst conductive layer comprises chemical vapor deposition.
 158. Themethod of claim 147, wherein said step of forming a second conductivelayer comprises chemical vapor deposition.
 159. The method of claim 147,wherein the first and the second conductive layers are doped polysiliconlayers.
 160. The method of claim 147, wherein the first insulating layeris a layer of material selected from the group consisting of siliconoxide, silicon nitride, silicon oxynitride, ON, NO, and ONO.
 161. Themethod of claim 147, wherein the second insulating layer is a layerdeposited silicon oxide or silicon oxide hardened by a nitrogentreatment.
 162. The method of claim 147, further comprising forming areset transistor adjacent to the photosensitive region having a dopedregion of a second conductivity type as a drain, the floating diffusionregion being the source of the reset transistor.
 163. The method ofclaim 147, further comprising forming an output transistor having a gateelectrically connected to the floating diffusion region.
 164. A methodof forming a stacked photogate for use in an imaging device, comprisingthe steps of: providing a semiconductor substrate having aphotosensitive region of a first conductivity type; forming a firstinsulating layer on the substrate and over the photosensitive region;forming a first conductive layer over the first insulating layeradjacent to the photosensitive region; forming a second insulating layerover the first conductive layer; patterning the first conductive layerand the second insulating layer to form a transfer gate and a reset gatefor a reset transistor; forming insulating spacers on the sides of thetransfer gate; forming a second conductive layer over the photosensitiveregion and extending over at least a portion of the transfer gate;forming a floating diffusion region of a second conductivity typebetween the transfer gate and the reset gate in the substrate, thefloating diffusion region being the source of the reset transistor; andforming a doped region of a second conductivity type adjacent to thereset gate, the doped region being the drain of the reset transistor.165. The method of claim 164, wherein the first conductivity type isp-type, and the second conductivity type is n-type.
 166. The method ofclaim 164, wherein the first conductivity type is n-type, and the secondconductivity type is p-type.
 167. The method of claim 164, wherein saidstep of forming a first insulating layer comprises thermal oxidation.168. The method of claim 164, wherein said step of forming a firstinsulating layer comprises deposition.
 169. The method of claim 164,wherein said step of forming a second insulating layer comprises thermaloxidation.
 170. The method of claim 164, wherein said step of forming asecond insulating layer comprises deposition.
 171. The method of claim164, wherein said step of forming a second insulating layer comprisesforming a silicon oxide layer and hardening the silicon oxide layer by anitrogen treatment.
 172. The method of claim 164, wherein said step offorming a first conductive layer comprises chemical vapor deposition.173. The method of claim 164, wherein said step of forming a secondconductive layer comprises chemical vapor deposition.
 174. The method ofclaim 164, wherein the first and the second conductive layers are dopedpolysilicon layers.
 175. The method of claim 164, wherein the firstinsulating layer is a layer of material selected from the groupconsisting of silicon oxide, silicon nitride, silicon oxynitride, ON,NO, and ONO.
 176. The method of claim 164, further comprising a step offorming a metal silicide layer on the first conductive layer prior tosaid step of forming a second insulating layer.
 177. The method of claim176, wherein said step of forming a metal silicide layer compriseschemical vapor deposition.
 178. The method of claim 176, wherein saidstep of forming a metal silicide layer further comprises forming a metallayer on the first conductive layer, and annealing the metal layer at atemperature within the range of approximately 300 to 800 degreesCelsius.
 179. The method of claim 176, wherein the metal silicide layeris a layer selected from the group consisting of tungsten silicide,titanium silicide, molybdenum silicide, tantalum silicide, platinumsilicide, palladium silicide, iridium silicide, and cobalt silicide.180. The method of claim 164, wherein said step of forming a floatingdiffusion region comprises ion implantation of at least one dopant intothe semiconductor substrate.
 181. The method of claim 164, furthercomprising forming an output transistor having a gate electricallyconnected to the floating diffusion region.